1. Field
Embodiments of the present invention generally relate to the field of operational amplifiers.
2. Background
The use of bipolar transistors in amplifiers has many managers over CMOS, such as large gain, better matching, and better noise performance. However, the finite input impedance of BJT amplifiers caused by the existence of these current can be a major limitation.
To reduce the input bias current for a bipolar differential pair, the concept of input bias current cancellation has been developed. Generally, input bias current cancellation involves supplying the same amount of bias current into the input internally. However, conventional methods of input bias current cancellation require large voltage headroom for the circuit to work properly (up to 2 V in some cases). Today's low-voltage applications do not have the luxury of such a generous voltage headroom.
More recent efforts have been made to reduce the voltage headroom required by input bias current cancellation circuits. For example, FIG. 1 illustrates the LT1678/LT1769 Op-Amp 100 manufactured by Linear Technology, Inc. In op-amp 100, in order to prevent input transistors Q1 and Q2 from going into saturation, the input voltage must not exceed the supply voltage (+VS in FIG. 1) minus the collector-emitter voltages of Q4 and Q5/Q6. In other words, op-amp 100 has a voltage overhead of 2VCE(sat). However, this voltage overhead is still unacceptable for lower voltage applications such as those using a 2 V power supply. Furthermore, a mismatch of VCE for Q4 and Q7 and the base current of the associated current mirror would cause a large amount of additional error. In some cases, applications require voltage headroom as low as 0.1 V.